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VHDL Code Library


All code on this page is released under an open-source license (LGPL). It is the 21th century reconfigurable logic equivalent of 74xx logic blocks (or CD40xx for those that liked CMOS). A collection of small building blocks that can help you to build larger FPGA designs. Everything here is written in VHDL as this is my prefered HDL (Hardware Description Language).

All code on this page is now also available on github as part of my FPGA examples project. The link to the project is https://github.com/pwsoft/fpga_examples.


Last update 20100714
Contains some support entities.

  • gen_counter, binary up/down counter with load and clear inputs.
  • gen_counter_signed, same as gen_counter but outputs signed values.
  • gen_counter_tb, testbench for the entities gen_counter and gen_counter_signed.
  • gen_pipeline, pipeline register of configurable depth and length.
  • gen_reset, powerup reset circuit with configurable reset pulse length and reset-button input.

Single bit Sigma-Delta audio DAC with configurable audio input width. The quality of the output isn't very high. It is only a first-order converter, but it uses only a few logic cells and a single FPGA pin. Connect a RC lowpass filter to the pin to reduce noise and improve the audio quality.

This file contains a timing generator for displaying graphics on a VGA screen. It doesn't generate any graphics itself. Only the sync signals, clocks and X/Y coordinates. File contains the following entities:

  • video_vga_master, a VGA timing and sync generator
  • video_dither, color dither circuit to trade resolution for higher color depth.
  • video_dither_rgb, dither circuit preconfigured to handle 24 bit RGB video and convert it to lower a color resolution.

Lowlevel device-drivers in VHDL for PS/2 keyboard and mouse. The keyboard driver delivers raw scan-codes and can update the status of the LEDs (caps-lock, num-lock and scroll-lock). The mouse driver supports both 2 button-mice and 3 button-mice with scroll-wheel. The scroll-wheel support can be turned off to reduce logic gate usage. Don't forget to set the correct value for ticksPerUsec (aka the clock-speed in MHz).

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